本次美国代写是一个Verilog集成电路系统设计的Lab

1. Design an unsigned fixed-point multiplier using Verilog HDL.

Input: clk, reset, 32-bits A, 32-bits B;

Output: 32-bits product.

Notes: For the fixed-point number, it separates to 16-bit integer bits and 16 fraction bits.

Fixed-point notation has an implied binary point between the integer and fraction bits, analogous to the
decimal point between the integer and fraction digits of an ordinary decimal number. For example,
01101100 shows a fixed-point with 4 integer digits and 4 fraction bits, which has the implied binary point
0110.1100. Its equivalent decimal value = 22 + 21 + 2-1 + 2-2 = 6.75.

Signed fixed-point numbers can use either two’s complement or sign/magnitude notation. For example, to
represent -2.375, first, its absolute value is 0010.0110. In sign/magnitude form, the most significant bit is
used to indicate the sign 1010.0110. In two’s complement representation it is formed by inverting the bits
of the absolute value and adding a 1 to the least significant (rightmost) bit (lsb), 1101.1001 + 0000.0001 =
1101.1010.

When you design this fixed-point multiplier, you can reuse your integer multiplier module in Lab1.

Step1: multiply the 2 fixed-point number a (n-bits), b (n-bits) as the integer number by integer multiplier
and get the (2n)-bit product.

Step2: truncate the product by the number of integer bit and fraction bit by implied binary point.

For example: 0010.1100 × 0010.1100

Product = integer multiplier (00101100, 00101100) = 0000011110010000

Find the binary point of product 00000111.10010000

Truncate the product by number of integer and fraction bits 00000111.10010000 = 0111.1001

Note: if there is overflow in product, just ignore it in your design.

Note: This multiplier is the most resource-consuming design; you are encouraged to explore more efficient
multiplier.

Tips: after shifting the multiplicand, the shifted left bits of multiplicand are all zeros, which is not worth
storing. Actually, the 64-bit multiplicand register can be replaced by a 32-bit multiplicand, so can the ALU.


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