# 这是一篇来自英国的关于解决电路电压相关问题的**作业代写**

**Answer FOUR questions **

**Answer only TWO questions from each of sections A and B **

**Each question is worth 25 marks **

**SECTION A: Attempt any TWO questions [50 marks] **

Q1 (a) Sketch a transistor circuit for a CMOS inverter, including a parasitic load capacitance (*C**L*), labeling its input, output and supply voltage connections. [5]

(b) The input is subjected to a square edge transition from input LOW to input HIGH at a time *t**0*. Sketch a timing diagram for the input and output waveforms illustrating output voltage value and corresponding times on the plot. [5]

(c) Using the answer for part (b) of this question, annotate the timing diagram with operating mode of both the NMOS and PMOS transistors, and the portion of the time axis for which the transistor modes you identify apply. [5]

(d) Using the timing diagram you have produced in parts (b) and (c) of this question, and the charging equation for a capacitor, show that the fall time for the voltage at the output of a CMOS inverter is given by:

*t **f *= *k**n**C**L /*b*n**V**D**D *

where *k**n *is a constant and all the other symbols have their usual meaning. [10]

Q2 a) Sketch the circuit diagram for a CMOS standard cell with the function:

*Z *= (*A*×*B*+*C*)× *D *[8]

(b) Transistor sizing (T-sizing) is used to optimize the performance of standard cells. The design is based on a standard cell library with a “unit” inverter with

*W**n *= *W**ni*, and *W**p *= *W**pi*. The ratio *W**pi*/*W**ni *= 2.

(I) Analyse the circuit you drew in part (a) to determine the stack depth of each block of transistors. [6]

(ii) T-size the circuit of part (a) to match the inverter’ output characteristics assuming a linear T-sizing method is used. State any design choices that you make to arrive at a solution. [8]

(iii) How would you modify the T-size calculation if the Fan-Out were to be doubled? [3]

Q3 (a) A pipelined system architecture is required to have the ability to arbitrarily shift data bits either to the left or the right, or not at all, in a single clock cycle. Sketch,using pass-transistor logic, a circuit that will do this. You may assume that there is an input and an output register associated with the device. [8]

(b) A simple digital multiplier relies on a process of successive shifting of data to the left, and addition.

(I) Show how you can express a *m*-bit unsigned binary number using radix-2 notation. [4]

(ii) By expressing two unsigned binary numbers *X *and *Y, *of length *m *and *n *respectively, in radix-2 notation, derive a formula for the product *Z *=*XY*. [8]

(c) Using your answer for part (b) of this question, write down the Boolean expression for the partial product that would appear in a logical implementation of the multiplier, and sketch the logic circuit, using conventional symbols, that would provide the required function. [5]

**SECTION B: Attempt any TWO questions [50 marks] **

Q4 (a) Draw the schematic of a simple CMOS current mirror employing p-channel transistors and explain its operation. [6]

(b) State the advantages of using a current mirror as an active load in integrated amplifier circuits. [3]

(c) A two-stage architecture is one of the most basic approaches for realising a CMOS operational amplifiers (Op-amp).

(i)Draw a clearly labeled schematic diagram of this type of Op-amp. [6]

(ii)Identify and briefly explain the functions of each stage of your circuit. [7]

(iii) Identify each current mirror in your circuit, stating its role in each case. [3]

Q5 (a) A popular digital-to-analogue converter (DAC) architecture, the potentiometric DAC, is based on selecting one tap of a segmented resistor string by a switch network.

(i)Draw the circuit diagram of a 2-bit potentiometric DAC. [4]

(ii)State the 3 main advantages of this type of DAC. What is its main disadvantage? [4]

(iii)Hence or otherwise, explain how this DAC architecture is exploited in high resolution converters. [2]

(b) Another popular DAC architecture is based on the resistor-ladder (R-2R) network. Draw the circuit diagram for a 3-bit R-2R based DAC. [5]

(c) By analysis of the circuit of Q5(b) show mathematically how the input bits of the DAC relate to the analogue output voltage. [6]

(d) What are the advantages and disadvantages of the R-2R DAC when compared to other DAC architectures (excluding the potentiometric DAC)? [4]

Q6 (a) A dc voltage of 2 V is applied to the input of the switched-capacitor circuit of Figure Q6 in which C1 is 10 pF. If a clock frequency of 200 kHz is used:

(I)What charge is transferred for each cycle of the two-phase clock, having the high ( ) clock and the low ( ) clock phases? [3]

(ii)What is the average current drawn from the input source? [3]

(iii)What is the equivalent input resistance? [3]

(iv)What would be the equivalent resistance if C1 were 200 pF? [3]

(b) The integrator function in a sigma-delta (-) analogue-to-digital converter (ADC) is realized using switched-capacitor (SC) techniques.

(I)Sketch the circuit diagram of a non-inverting SC integrator.[3]

(ii)List the advantages of SC integrators compared to conventional resistorcapacitor integrators. [3]

(c) The signal-to-noise ratio of a first order - ADC is = 6.02(n + 1.5m) – 3.41 dB,where the basic ADC is n-bit and the oversampling ratio is 2m. What sample rate is required to obtain 16-bit resolution if the system uses a 1-bit ADC and the Nyquist sampling rate is 25 kHz? [3]

(d) What are the main advantages of - ADCs? [4]

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